All integrated circuits are subject to parasitic capacitances and capacitive coupling. Parasitic substrate capacitance and capacitive coupling can impede the operating speed or slew rate of the circuit. The slew rate of each node of the circuit is determined by the current available to charge a node's capacitance divided by the capacitance at that node. For a circuit like an operational amplifier (Op Amp), the slew rate for the circuit is approximately equal to the slowest of the slew rates of the nodes in the signal path divided by the voltage gain from the output back to that node.
Some circuits, such as Op Amps, have large power supply voltages (.about.30V) and speed requirements. In order to obtain tighter packing of devices for such circuits, it is advantageous to form the circuit on a dielectrically isolated device layer. This is sometimes referred to as silicon-on-insulator or SOI. SOI replaces the large junctions of P- and N-type material with small regions of insulating material having high breakdown voltages. An SOI substrate comprises a carrier wafer substrate separated from the active silicon layer by a buried oxide layer. The decrease in silicon area reduces the area dependent capacitances, wiring capacitances, and distance related resistances. However, parasitic capacitances still exist which affect the slew rate, stability and maximum operating frequency of the circuits.
One way to improve the slew rate of an Op Amp on an SOI substrate is to reduce the capacitance at the restricting node of the amplifier. Prior art trench isolated technologies have relied on a single trench for isolation. Junction isolated processes rely on spacing between devices, guard rings and careful interconnect to avoid capacitive coupling, but these issues do not address substrate capacitance. A prior art trench isolated structure is shown in FIG. 1. In a dielectrically isolated technology, there exists a parasitic capacitance 10 from the collector of a bipolar transistor of transistor region 12 across the buried oxide 20 to the carrier wafer substrate 14 and another parasitic capacitance 16 to the floating (not electrically connected) silicon 18 across the dielectric 20 from the collector region. The capacitance between a component and the carrier substrate is primarily a function of the trench-enclosed area and the dielectric thickness. Thus, the process technology must be altered in order to have a significant effect on the parasitic capacitance of this structure. However, the process technology is often developed by balancing the needs of various circuits. Therefore, a method for reducing the parasitic capacitance and capacitive coupling that does not require changes to the process technology is desired.